A dual-diode based ESD protection network is a common and attractive approach for LCD-driver and power management products in high voltage applications. However, a challenge exists as how to provide an efficient and latch-up free power-rail ESD protection based on a dual-diode based ESD protection network.
A traditional ESD protection circuit in a high voltage process is shown in FIG. 1. Whole chip ESD performance is dependent on the performance of ESD power clamp 12. Avoidance of latch-up is an objective in designing a high voltage application. Latch-up is a term used to describe a short circuit that can occur in an improperly designed circuit, wherein inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit occurs. Triggering of a parasitic structure can disrupt proper functioning of the circuit or lead to its destruction by overcurrent.
Various methods traditionally have been implemented for power-rail ESD device protection. Different high voltage power-rail ESD protection arrangements have comparative advantages and disadvantages. For example, ggNMOS (gate-grounded NMOS) circuitry has been used as a power-rail ESD protection device. Such circuitry, however, tends to have latch-up problems due to inherent strong snapback characteristic. Alternatively, the use of gpPMOS as a power-rail ESD protection device can be latch-up free due to non-snapback characteristic, but has a drawback of low efficiency in protecting victims due to low ESD performance.
An attractive and compact size power-rail ESD protection device is RC-based NMOS. However, the RC-based NMOS has inherent drawbacks such as strong snapback behavior that will limit the ESD performance of the RC-based NMOS ESD power clamp circuit once entering the snapback regime. ESD performance of traditional RC-based NMOS ESD power clamps is similar to that of ggNMOS implementations. When a traditional RC-based NMOS power clamp enters snapback regime, the device will suffer permanent damage.
A need thus exists for an RC-based NMOS power-rail ESD protection circuit with high snapback voltage behavior to achieve efficient, ESD robust and compact size ESD power clamp in high voltage process. Such a device should have a low likelihood of latch-up with high snapback voltage characteristic.